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1 parent dc6b748 commit f8c1edfCopy full SHA for f8c1edf
source/hic_hal/nxp/lpc4322/board_LPC43xx.c
@@ -20,24 +20,7 @@
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*/
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#include "sdk.h"
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-#include "lpc43xx_cgu.h"
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void sdk_init(void)
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{
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- /* Set core clock to 120MHz */
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- CGU_Init(120000000);
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- /* Set up USB0 clock */
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- /* Disable PLL first */
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- CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE);
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-
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- /* the usb core require output clock = 480MHz */
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- if (CGU_SetPLL0() != CGU_ERROR_SUCCESS) {
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- while (1);
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- }
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- CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
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- /* Enable PLL after all setting is done */
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- CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);
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- /* Turn on the USB0PHY */
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- LPC_CREG->CREG0 &= ~(1 << 5);
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}
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