From 326abe48a58fdf4dc5fdfc936f97e81a52588a43 Mon Sep 17 00:00:00 2001
From: Kevincooool <33611679+Kevincoooool@users.noreply.github.com>
Date: Sat, 20 Mar 2021 16:00:11 +0800
Subject: [PATCH 1/2] Add software auto reset
---
source/hic_hal/atmel/sam3u2c/DAP_config.h | 22 +-
source/hic_hal/stm32/stm32f103xb/DAP_config.h | 279 +++++++++---------
2 files changed, 153 insertions(+), 148 deletions(-)
diff --git a/source/hic_hal/atmel/sam3u2c/DAP_config.h b/source/hic_hal/atmel/sam3u2c/DAP_config.h
index bb39b9aa46..1aadd54b02 100644
--- a/source/hic_hal/atmel/sam3u2c/DAP_config.h
+++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h
@@ -401,14 +401,22 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
}
}
#else
-__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+extern uint8_t swd_init_debug(void);
+extern uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size);
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
{
- if (bit & 1) {
- PIN_nRESET_PORT->PIO_SODR = PIN_nRESET;
-
- } else {
- PIN_nRESET_PORT->PIO_CODR = PIN_nRESET;
- }
+ if (bit & 1)
+ {
+ PIN_nRESET_PORT->PIO_SODR = PIN_nRESET;
+ }
+ else
+ {
+ PIN_nRESET_PORT->PIO_CODR = PIN_nRESET;
+
+ swd_init_debug();
+ uint32_t swd_mem_write_data = 0x05FA0000 | 0x4;
+ swd_write_memory(0xE000ED0C, (uint8_t *)&swd_mem_write_data, 4);
+ }
}
#endif
///@}
diff --git a/source/hic_hal/stm32/stm32f103xb/DAP_config.h b/source/hic_hal/stm32/stm32f103xb/DAP_config.h
index ce250bccc9..6c67209f86 100644
--- a/source/hic_hal/stm32/stm32f103xb/DAP_config.h
+++ b/source/hic_hal/stm32/stm32f103xb/DAP_config.h
@@ -43,7 +43,7 @@ Provides definitions about:
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
-#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
@@ -51,131 +51,129 @@ Provides definitions about:
/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// requrired.
-#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
-#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
-#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
-#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimized the communication performance with the
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
-#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimized the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
-#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
/// Maximum SWO UART Baudrate
-#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
/// SWO Trace Buffer Size.
-#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
/// SWO Streaming Trace.
-#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
-#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
-
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor and Device Name string is stored which
/// may be used by the debugger or IDE to configure device parameters.
-#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
#if TARGET_DEVICE_FIXED
-#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
-#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
#endif
///@}
-
-__STATIC_INLINE void pin_out_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
+__STATIC_INLINE void pin_out_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit)
{
- if(pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
- GPIOx->CRH |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit-8) << 2) );
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit) << 2) );
- }
+ if (pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
+ GPIOx->CRH |= (((uint32_t)(0x00 | 0x03) & 0x0F) << ((pin_bit - 8) << 2));
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= (((uint32_t)(0x00 | 0x03) & 0x0F) << ((pin_bit) << 2));
+ }
}
-__STATIC_INLINE void pin_out_od_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
+__STATIC_INLINE void pin_out_od_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit)
{
- if(pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
- GPIOx->CRH |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit-8) << 2) );
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit) << 2) );
- }
+ if (pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
+ GPIOx->CRH |= (((uint32_t)(0x04 | 0x03) & 0x0F) << ((pin_bit - 8) << 2));
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= (((uint32_t)(0x04 | 0x03) & 0x0F) << ((pin_bit) << 2));
+ }
}
-__STATIC_INLINE void pin_in_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit, uint8_t mode)
+__STATIC_INLINE void pin_in_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit, uint8_t mode)
{
- uint8_t config;
- if(mode == 1)
- config = 0x08; //Up
- else if(mode == 2)
- config = 0x08; //down
- else
- config = 0x00; //GPIO_Mode_AIN
-
- if(pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
- GPIOx->CRH |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit-8) << 2) );
- if(mode == 1)
- GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
- else if(mode == 2)
- GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit) << 2) );
- if(mode == 1)
- GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
- else if(mode == 2)
- GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
- }
+ uint8_t config;
+ if (mode == 1)
+ config = 0x08; //Up
+ else if (mode == 2)
+ config = 0x08; //down
+ else
+ config = 0x00; //GPIO_Mode_AIN
+
+ if (pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
+ GPIOx->CRH |= (((uint32_t)(config)&0x0F) << ((pin_bit - 8) << 2));
+ if (mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if (mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= (((uint32_t)(config)&0x0F) << ((pin_bit) << 2));
+ if (mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if (mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
}
//**************************************************************************************************
/**
@@ -212,7 +210,6 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
-
// Configure DAP I/O pins ------------------------------
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
@@ -234,17 +231,17 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
*/
__STATIC_INLINE void PORT_SWD_SETUP(void)
{
- // Set SWCLK HIGH
- pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
- // Set SWDIO HIGH
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
-
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
- // Set RESET HIGH
- pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);//TODO - fix reset logic
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ // Set SWCLK HIGH
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ // Set SWDIO HIGH
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+ // Set RESET HIGH
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit); //TODO - fix reset logic
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
}
/** Disable JTAG/SWD I/O Pins.
@@ -253,9 +250,9 @@ Disables the DAP Hardware I/O pins which configures:
*/
__STATIC_INLINE void PORT_OFF(void)
{
- pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
- pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
+ pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
}
// SWCLK/TCK I/O pin -------------------------------------
@@ -265,7 +262,7 @@ __STATIC_INLINE void PORT_OFF(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
{
- return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
+ return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
}
/** SWCLK/TCK I/O pin: Set Output to High.
@@ -273,7 +270,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
{
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
}
/** SWCLK/TCK I/O pin: Set Output to Low.
@@ -281,7 +278,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
{
- SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
+ SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
}
// SWDIO/TMS Pin I/O --------------------------------------
@@ -291,7 +288,7 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
{
- return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
}
/** SWDIO/TMS I/O pin: Set Output to High.
@@ -299,7 +296,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
{
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
}
/** SWDIO/TMS I/O pin: Set Output to Low.
@@ -307,7 +304,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
{
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
@@ -315,7 +312,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
{
- return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
@@ -323,10 +320,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
{
- if (bit & 1)
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
- else
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ if (bit & 1)
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ else
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -335,8 +332,8 @@ called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
{
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -345,11 +342,10 @@ called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
{
- pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
}
-
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
@@ -357,7 +353,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
/** TDI I/O pin: Set Output.
@@ -365,10 +361,9 @@ __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
-
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
@@ -376,10 +371,9 @@ __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
-
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
@@ -387,7 +381,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
/** nTRST I/O pin: Set Output.
@@ -397,7 +391,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
// nRESET Pin I/O------------------------------------------
@@ -407,7 +401,7 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
{
- return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
+ return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
}
/** nRESET I/O pin: Set Output.
@@ -416,15 +410,20 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
- 1: release device hardware reset.
*/
// TODO - sw specific implementation should be created
-
-__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+extern uint8_t swd_init_debug(void);
+extern uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size);
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
{
- if (bit & 1)
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
- else
- nRESET_PIN_PORT->BRR = nRESET_PIN;
+ if (bit & 1)
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ else
+ nRESET_PIN_PORT->BRR = nRESET_PIN;
+
+ swd_init_debug();
+ uint32_t swd_mem_write_data = 0x05FA0000 | 0x4;
+ swd_write_memory(0xE000ED0C, (uint8_t *)&swd_mem_write_data, 4);
+}
}
-
//**************************************************************************************************
/**
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
@@ -445,10 +444,10 @@ It is recommended to provide the following LEDs for status indication:
*/
__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
{
- if (bit & 1)
- CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
- else
- CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;// LED off
+ if (bit & 1)
+ CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
+ else
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN; // LED off
}
/** Debug Unit: Set status Target Running LED.
@@ -458,12 +457,11 @@ __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
*/
__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
///@}
-
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
@@ -479,13 +477,13 @@ default, the DWT timer is used. The frequency of this timer is configured with
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
-__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
- return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+__STATIC_INLINE uint32_t TIMESTAMP_GET(void)
+{
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
}
///@}
-
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
@@ -505,25 +503,25 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
*/
__STATIC_INLINE void DAP_SETUP(void)
{
- /* Enable port clock */
- __HAL_RCC_GPIOA_CLK_ENABLE();
- __HAL_RCC_GPIOB_CLK_ENABLE();
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOD_CLK_ENABLE();
- /* Configure I/O pin SWCLK */
- pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ /* Enable port clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /* Configure I/O pin SWCLK */
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
- pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
- pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
- CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
+ pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
}
/** Reset Target Device with custom specific I/O pin or command sequence.
@@ -535,10 +533,9 @@ when a device needs a time-critical unlock sequence that enables the debug port.
*/
__STATIC_INLINE uint32_t RESET_TARGET(void)
{
- return (0); // change to '1' when a device reset sequence is implemented
+ return (0); // change to '1' when a device reset sequence is implemented
}
///@}
-
#endif /* __DAP_CONFIG_H__ */
From dbf26f9fff55dc65f5d8a3c0dcf9a1b06e6e15b4 Mon Sep 17 00:00:00 2001
From: Kevincooool <33611679+Kevincoooool@users.noreply.github.com>
Date: Sat, 20 Mar 2021 16:03:15 +0800
Subject: [PATCH 2/2] Update DAP_config.h
---
source/hic_hal/stm32/stm32f103xb/DAP_config.h | 274 +++++++++---------
1 file changed, 141 insertions(+), 133 deletions(-)
diff --git a/source/hic_hal/stm32/stm32f103xb/DAP_config.h b/source/hic_hal/stm32/stm32f103xb/DAP_config.h
index 6c67209f86..bdc1b0a8f8 100644
--- a/source/hic_hal/stm32/stm32f103xb/DAP_config.h
+++ b/source/hic_hal/stm32/stm32f103xb/DAP_config.h
@@ -43,7 +43,7 @@ Provides definitions about:
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
-#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
@@ -51,129 +51,131 @@ Provides definitions about:
/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// requrired.
-#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
-#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
-#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
-#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimized the communication performance with the
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
-#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimized the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
-#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
/// Maximum SWO UART Baudrate
-#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of Capabilities.
-#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
/// SWO Trace Buffer Size.
-#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
/// SWO Streaming Trace.
-#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
-#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor and Device Name string is stored which
/// may be used by the debugger or IDE to configure device parameters.
-#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
#if TARGET_DEVICE_FIXED
-#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
-#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
#endif
///@}
-__STATIC_INLINE void pin_out_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit)
+
+__STATIC_INLINE void pin_out_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
{
- if (pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
- GPIOx->CRH |= (((uint32_t)(0x00 | 0x03) & 0x0F) << ((pin_bit - 8) << 2));
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= (((uint32_t)(0x00 | 0x03) & 0x0F) << ((pin_bit) << 2));
- }
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit-8) << 2) );
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit) << 2) );
+ }
}
-__STATIC_INLINE void pin_out_od_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit)
+__STATIC_INLINE void pin_out_od_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
{
- if (pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
- GPIOx->CRH |= (((uint32_t)(0x04 | 0x03) & 0x0F) << ((pin_bit - 8) << 2));
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= (((uint32_t)(0x04 | 0x03) & 0x0F) << ((pin_bit) << 2));
- }
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit-8) << 2) );
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit) << 2) );
+ }
}
-__STATIC_INLINE void pin_in_init(GPIO_TypeDef *GPIOx, uint8_t pin_bit, uint8_t mode)
+__STATIC_INLINE void pin_in_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit, uint8_t mode)
{
- uint8_t config;
- if (mode == 1)
- config = 0x08; //Up
- else if (mode == 2)
- config = 0x08; //down
- else
- config = 0x00; //GPIO_Mode_AIN
-
- if (pin_bit >= 8)
- {
- GPIOx->CRH &= ~(0x0000000F << ((pin_bit - 8) << 2));
- GPIOx->CRH |= (((uint32_t)(config)&0x0F) << ((pin_bit - 8) << 2));
- if (mode == 1)
- GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
- else if (mode == 2)
- GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
- }
- else
- {
- GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
- GPIOx->CRL |= (((uint32_t)(config)&0x0F) << ((pin_bit) << 2));
- if (mode == 1)
- GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
- else if (mode == 2)
- GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
- }
+ uint8_t config;
+ if(mode == 1)
+ config = 0x08; //Up
+ else if(mode == 2)
+ config = 0x08; //down
+ else
+ config = 0x00; //GPIO_Mode_AIN
+
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit-8) << 2) );
+ if(mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if(mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit) << 2) );
+ if(mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if(mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
}
//**************************************************************************************************
/**
@@ -210,6 +212,7 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
+
// Configure DAP I/O pins ------------------------------
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
@@ -231,17 +234,17 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
*/
__STATIC_INLINE void PORT_SWD_SETUP(void)
{
- // Set SWCLK HIGH
- pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
- // Set SWDIO HIGH
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
-
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
- // Set RESET HIGH
- pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit); //TODO - fix reset logic
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ // Set SWCLK HIGH
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ // Set SWDIO HIGH
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+ // Set RESET HIGH
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);//TODO - fix reset logic
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
}
/** Disable JTAG/SWD I/O Pins.
@@ -250,9 +253,9 @@ Disables the DAP Hardware I/O pins which configures:
*/
__STATIC_INLINE void PORT_OFF(void)
{
- pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
- pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
+ pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
}
// SWCLK/TCK I/O pin -------------------------------------
@@ -262,7 +265,7 @@ __STATIC_INLINE void PORT_OFF(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
{
- return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
+ return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
}
/** SWCLK/TCK I/O pin: Set Output to High.
@@ -270,7 +273,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
{
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
}
/** SWCLK/TCK I/O pin: Set Output to Low.
@@ -278,7 +281,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
{
- SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
+ SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
}
// SWDIO/TMS Pin I/O --------------------------------------
@@ -288,7 +291,7 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
{
- return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
}
/** SWDIO/TMS I/O pin: Set Output to High.
@@ -296,7 +299,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
{
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
}
/** SWDIO/TMS I/O pin: Set Output to Low.
@@ -304,7 +307,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
{
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
@@ -312,7 +315,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
{
- return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
@@ -320,10 +323,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
{
- if (bit & 1)
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
- else
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ if (bit & 1)
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ else
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -332,8 +335,8 @@ called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
{
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -342,10 +345,11 @@ called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
{
- pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
}
+
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
@@ -353,7 +357,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
/** TDI I/O pin: Set Output.
@@ -361,9 +365,10 @@ __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
+
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
@@ -371,9 +376,10 @@ __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
+
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
@@ -381,7 +387,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
{
- return (0); // Not available
+ return (0); // Not available
}
/** nTRST I/O pin: Set Output.
@@ -391,7 +397,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
// nRESET Pin I/O------------------------------------------
@@ -401,7 +407,7 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
{
- return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
+ return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
}
/** nRESET I/O pin: Set Output.
@@ -415,14 +421,14 @@ extern uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size);
__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
{
if (bit & 1)
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
- else
- nRESET_PIN_PORT->BRR = nRESET_PIN;
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ else
+ nRESET_PIN_PORT->BRR = nRESET_PIN;
- swd_init_debug();
- uint32_t swd_mem_write_data = 0x05FA0000 | 0x4;
- swd_write_memory(0xE000ED0C, (uint8_t *)&swd_mem_write_data, 4);
-}
+ swd_init_debug();
+ uint32_t swd_mem_write_data = 0x05FA0000 | 0x4;
+ swd_write_memory(0xE000ED0C, (uint8_t *)&swd_mem_write_data, 4);
+ }
}
//**************************************************************************************************
/**
@@ -444,10 +450,10 @@ It is recommended to provide the following LEDs for status indication:
*/
__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
{
- if (bit & 1)
- CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
- else
- CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN; // LED off
+ if (bit & 1)
+ CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
+ else
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;// LED off
}
/** Debug Unit: Set status Target Running LED.
@@ -457,11 +463,12 @@ __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
*/
__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
{
- ; // Not available
+ ; // Not available
}
///@}
+
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
@@ -477,13 +484,13 @@ default, the DWT timer is used. The frequency of this timer is configured with
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
-__STATIC_INLINE uint32_t TIMESTAMP_GET(void)
-{
- return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
}
///@}
+
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
@@ -503,25 +510,25 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
*/
__STATIC_INLINE void DAP_SETUP(void)
{
- /* Enable port clock */
- __HAL_RCC_GPIOA_CLK_ENABLE();
- __HAL_RCC_GPIOB_CLK_ENABLE();
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOD_CLK_ENABLE();
- /* Configure I/O pin SWCLK */
- pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
- SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ /* Enable port clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /* Configure I/O pin SWCLK */
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
- pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
- SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
- pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
- pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
- nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
- pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
- CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
+ pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
}
/** Reset Target Device with custom specific I/O pin or command sequence.
@@ -533,9 +540,10 @@ when a device needs a time-critical unlock sequence that enables the debug port.
*/
__STATIC_INLINE uint32_t RESET_TARGET(void)
{
- return (0); // change to '1' when a device reset sequence is implemented
+ return (0); // change to '1' when a device reset sequence is implemented
}
///@}
+
#endif /* __DAP_CONFIG_H__ */