v2.3

Nic30 · Nic30 · commit 8cc16ca04a40 · 2021-07-02T09:08:51.000+02:00
diff --git a/setup.py b/setup.py
@@ -22,7 +22,7 @@
         # '-DCMAKE_BUILD_TYPE=Debug'
     ],
     name='hdlConvertor',
-    version='2.2',
+    version='2.3',
     description='VHDL and System Verilog parser written in c++',
     long_description=long_description,
     long_description_content_type="text/markdown",
