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Design Rule Check - 28pins_pcb.drc
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Protel Design System Design Rule Check
PCB File : C:\Users\Public\Documents\Altium\28pins_project\28pins_pcb.PcbDoc
Date : 27-12-2024
Time : 00:13:54
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.3mm) (IsRegion),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.4mm) (Max=4mm) (Preferred=0.4mm) (InNet('+*') or InNet('GND'))
Rule Violations :0
Processing Rule : Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.3mm) (All)
Rule Violations :0
Processing Rule : Routing Topology Rule(Topology=Shortest) (All)
Rule Violations :0
Processing Rule : Routing Layers(All)
Rule Violations :0
Processing Rule : Routing Via (MinHoleWidth=0.3mm) (MaxHoleWidth=0.3mm) (PreferredHoleWidth=0.3mm) (MinWidth=0.6mm) (MaxWidth=0.6mm) (PreferedWidth=0.6mm) (All)
Rule Violations :0
Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) and Width Constraints (Min=0.381mm) (Max=0.381mm) (Prefered=0.381mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.2mm) (Max=10mm) (All)
Rule Violations :0
Processing Rule : Pads and Vias to follow the Drill pairs settings
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.3mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.1mm) (IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('MH4')),(InComponent('FID4') or InComponent('J4'))
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('R27')),(InComponent('R28'))
Violation between Component Clearance Constraint: (Collision) Between SMT Small Component R27-0R (33.3mm,7.5mm) on L1 And SMT Small Component R28-0R (33.3mm,5.6mm) on L1
Rule Violations :1
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('SW2')),(InComponent('FID1'))
Violation between Component Clearance Constraint: (Collision) Between Component SW2-1825910-6 (22.4mm,4.8mm) on L1 And SMT Small Component FID1-FID_1MMC (22.4mm,4.6mm) on L1
Rule Violations :1
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('SCKT FOR U1')),(InComponent('U1'))
Violation between Component Clearance Constraint: (Collision) Between DIP Component U1-ATMEGA328P-PU (62.065mm,20.193mm) on L1 And SMT Small Component SCKT FOR U1-28-DIP Socket (62.065mm,20.193mm) on L1
Rule Violations :1
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.2mm, Vertical Gap = 0.2mm ) (All),(All)
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('MH2')),(InComponent('J2'))
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 3
Waived Violations : 0
PCB Health Issues : 0
Time Elapsed : 00:00:01