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Merge pull request ARMmbed#14687 from JeanMarcR/STM32L5_NEW_CUBE
STM32L5 update drivers version to CUBE V1.4.0
2 parents 3dd9140 + b2b9c3d commit 9135966

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‎targets/TARGET_STM/README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
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| L0 | 1.12.0 | https://github.com/STMicroelectronics/STM32CubeL0 |
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| L1 | 1.10.2 | https://github.com/STMicroelectronics/STM32CubeL1 |
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| L4 | 1.17.0 | https://github.com/STMicroelectronics/STM32CubeL4 |
76-
| L5 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeL5 |
76+
| L5 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeL5 |
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| WB | 1.11.1 | https://github.com/STMicroelectronics/STM32CubeWB |
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| WL | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeWL |
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‎targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -164,8 +164,8 @@ typedef enum
164164
HASH_IRQn = 96, /*!< HASH global interrupt */
165165
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
166166
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
167-
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
168-
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
167+
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
168+
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
169169
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
170170
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
171171
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
@@ -1022,7 +1022,9 @@ typedef struct
10221022
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
10231023
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
10241024
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1025-
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
1025+
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
1026+
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1027+
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
10261028
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
10271029
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
10281030
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
@@ -13974,9 +13976,20 @@ typedef struct
1397413976
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
1397513977

1397613978
/******************** Bits definition for TAMP_COUNTR register ***************/
13977-
#define TAMP_COUNTR_Pos (16U)
13978-
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
13979-
#define TAMP_COUNTR TAMP_COUNTR_Msk
13979+
#define TAMP_COUNTR_Pos (16U)
13980+
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
13981+
#define TAMP_COUNTR TAMP_COUNTR_Msk
13982+
13983+
/******************** Bits definition for TAMP_CFGR register *****************/
13984+
#define TAMP_CFGR_TMONEN_Pos (1U)
13985+
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
13986+
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
13987+
#define TAMP_CFGR_VMONEN_Pos (2U)
13988+
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
13989+
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
13990+
#define TAMP_CFGR_WUTMONEN_Pos (3U)
13991+
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
13992+
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk
1398013993

1398113994
/******************** Bits definition for TAMP_BKP0R register ***************/
1398213995
#define TAMP_BKP0R_Pos (0U)

‎targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,8 @@ typedef enum
166166
PKA_IRQn = 97, /*!< PKA global interrupt */
167167
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
168168
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
169-
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
170-
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
169+
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
170+
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
171171
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
172172
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
173173
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
@@ -1096,7 +1096,9 @@ typedef struct
10961096
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
10971097
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
10981098
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1099-
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
1099+
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
1100+
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1101+
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
11001102
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
11011103
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
11021104
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
@@ -14713,9 +14715,20 @@ typedef struct
1471314715
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
1471414716

1471514717
/******************** Bits definition for TAMP_COUNTR register ***************/
14716-
#define TAMP_COUNTR_Pos (16U)
14717-
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
14718-
#define TAMP_COUNTR TAMP_COUNTR_Msk
14718+
#define TAMP_COUNTR_Pos (16U)
14719+
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
14720+
#define TAMP_COUNTR TAMP_COUNTR_Msk
14721+
14722+
/******************** Bits definition for TAMP_CFGR register *****************/
14723+
#define TAMP_CFGR_TMONEN_Pos (1U)
14724+
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
14725+
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
14726+
#define TAMP_CFGR_VMONEN_Pos (2U)
14727+
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
14728+
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
14729+
#define TAMP_CFGR_WUTMONEN_Pos (3U)
14730+
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
14731+
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk
1471914732

1472014733
/******************** Bits definition for TAMP_BKP0R register ***************/
1472114734
#define TAMP_BKP0R_Pos (0U)

‎targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@
7979
*/
8080
#define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
8181
#define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
82-
#define __STM32L5_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
82+
#define __STM32L5_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
8383
#define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
8484
#define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
8585
|(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\

‎targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ target_sources(mbed-stm32l5cube-fw
6161
STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c
6262
STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c
6363
STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.c
64+
STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c
6465
STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c
6566
STM32L5xx_HAL_Driver/stm32l5xx_hal_spi_ex.c
6667
STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c
@@ -82,6 +83,7 @@ target_sources(mbed-stm32l5cube-fw
8283
STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c
8384
STM32L5xx_HAL_Driver/stm32l5xx_ll_gpio.c
8485
STM32L5xx_HAL_Driver/stm32l5xx_ll_i2c.c
86+
STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c
8587
STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c
8688
STM32L5xx_HAL_Driver/stm32l5xx_ll_lpuart.c
8789
STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.c

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