@@ -164,8 +164,8 @@ typedef enum
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HASH_IRQn = 96, /*!< HASH global interrupt */
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LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
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SPI3_IRQn = 99, /*!< SPI3 global interrupt */
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- I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
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- I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
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+ I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
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+ I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
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DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
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DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
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DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
@@ -1022,7 +1022,9 @@ typedef struct
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__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
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__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
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__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
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- uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
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+ uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
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+ __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
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+ uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
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__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
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__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
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__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
@@ -13974,9 +13976,20 @@ typedef struct
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#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
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/******************** Bits definition for TAMP_COUNTR register ***************/
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- #define TAMP_COUNTR_Pos (16U)
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- #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
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- #define TAMP_COUNTR TAMP_COUNTR_Msk
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+ #define TAMP_COUNTR_Pos (16U)
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+ #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
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+ #define TAMP_COUNTR TAMP_COUNTR_Msk
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+
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+ /******************** Bits definition for TAMP_CFGR register *****************/
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+ #define TAMP_CFGR_TMONEN_Pos (1U)
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+ #define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
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+ #define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
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+ #define TAMP_CFGR_VMONEN_Pos (2U)
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+ #define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
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+ #define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
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+ #define TAMP_CFGR_WUTMONEN_Pos (3U)
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+ #define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
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+ #define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk
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/******************** Bits definition for TAMP_BKP0R register ***************/
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#define TAMP_BKP0R_Pos (0U)
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