@@ -11716,7 +11716,6 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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TR::Register *vtmp2Reg = cg->allocateRegister(TR_VRF);
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TR::Register *storeReg = cg->allocateRegister();
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- TR::Register *maskReg = cg->allocateRegister();
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TR::LabelSymbol *VSXLabel = generateLabelSymbol(cg);
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TR::LabelSymbol *serialPrepLabel = generateLabelSymbol(cg);
@@ -11817,16 +11816,20 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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// --- serialPrepLabel to deal with whatever remains
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generateLabelInstruction(cg, TR::InstOpCode::label, node, serialPrepLabel);
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- // do we have enough elements to use the unroll loop?
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, tempReg, lengthReg, -3);
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+
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+ // calculate the count for unroll loop
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+ generateTrg1Src2Instruction(cg, TR::InstOpCode::subf, node, tempReg, indexReg, lengthReg);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::srawi, node, tempReg, tempReg, 2);
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+ generateSrc1Instruction(cg, TR::InstOpCode::mtctr, node, tempReg);
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+
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// we need to use 4 individual masks instead for countPositves() in LE
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if (!isLE || !isCountPositives)
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{
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- // we want to load 0x80808080 in to maskReg , but lis was designed for signed values,
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+ // we want to load 0x80808080 in to tempReg , but lis was designed for signed values,
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// and would throw an error for 0x8080, yet it could accept the equivalent negative value of it;
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// we don't worry about sign extension since the upper word should be 0 in storeReg after lwzx
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- generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, maskReg , -32640);
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, maskReg, maskReg , 0x8080);
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+ generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, tempReg , -32640);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, tempReg, tempReg , 0x8080);
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}
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generateLabelInstruction(cg, TR::InstOpCode::label, node, serialUnrollLabel);
@@ -11840,26 +11843,26 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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{
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if (isLE)
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{
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andi_r, node, maskReg , storeReg, 0x80);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andi_r, node, tempReg , storeReg, 0x80);
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generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, endLabel, cr0);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, indexReg, indexReg, 1);
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andi_r, node, maskReg , storeReg, 0x8000);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andi_r, node, tempReg , storeReg, 0x8000);
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generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, endLabel, cr0);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, indexReg, indexReg, 1);
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andis_r, node, maskReg , storeReg, 0x80);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andis_r, node, tempReg , storeReg, 0x80);
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generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, endLabel, cr0);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, indexReg, indexReg, 1);
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- generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andis_r, node, maskReg , storeReg, 0x8000);
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+ generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::andis_r, node, tempReg , storeReg, 0x8000);
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generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, endLabel, cr0);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, indexReg, indexReg, 1);
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}
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else
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{
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- generateTrg1Src2Instruction(cg, TR::InstOpCode::AND, node, storeReg, storeReg, maskReg );
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+ generateTrg1Src2Instruction(cg, TR::InstOpCode::AND, node, storeReg, storeReg, tempReg );
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generateTrg1Src1Instruction(cg, TR::InstOpCode::cntlzw, node, storeReg, storeReg);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::srawi, node, storeReg, storeReg, 3);
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generateTrg1Src2Instruction(cg, TR::InstOpCode::add, node, indexReg, storeReg, indexReg);
@@ -11870,13 +11873,13 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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}
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else
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{
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- generateTrg1Src2Instruction(cg, TR::InstOpCode::AND, node, storeReg, storeReg, maskReg );
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+ generateTrg1Src2Instruction(cg, TR::InstOpCode::AND, node, storeReg, storeReg, tempReg );
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi4, node, cr6, storeReg, 0);
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// this label happens to work
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generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, matchLabel, cr6);
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generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, indexReg, indexReg, 4);
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}
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- generateLabelInstruction (cg, TR::InstOpCode::b , node, serialUnrollLabel);
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+ generateConditionalBranchInstruction (cg, TR::InstOpCode::bdnz , node, serialUnrollLabel, cr6 );
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generateLabelInstruction(cg, TR::InstOpCode::label, node, serialLabel);
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generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp4, node, cr6, indexReg, lengthReg);
@@ -11908,7 +11911,7 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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// end
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TR::RegisterDependencyConditions *deps =
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- new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 11 , cg->trMemory());
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+ new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 10 , cg->trMemory());
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deps->addPostCondition(startReg, TR::RealRegister::NoReg);
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deps->getPostConditions()->getRegisterDependency(deps->getAddCursorForPost() - 1)->setExcludeGPR0();
@@ -11930,7 +11933,6 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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deps->addPostCondition(vtmp2Reg, TR::RealRegister::NoReg);
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deps->addPostCondition(storeReg, TR::RealRegister::NoReg);
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- deps->addPostCondition(maskReg, TR::RealRegister::NoReg);
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generateDepLabelInstruction(cg, TR::InstOpCode::label, node, endLabel, deps);
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@@ -11955,7 +11957,6 @@ static TR::Register *inlineStringCodingHasNegativesOrCountPositives(TR::Node *no
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cg->stopUsingRegister(vtmp2Reg);
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cg->stopUsingRegister(storeReg);
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- cg->stopUsingRegister(maskReg);
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for (int32_t i = 0; i < node->getNumChildren(); i++)
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{
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