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‎Lab7/binary_bcd.vhd

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity binary_bcd is
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generic(N: positive := 6);
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port(
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clk, reset: in std_logic;
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binary_in: in std_logic_vector(N-1 downto 0);
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-- bcd0, bcd1, bcd2, bcd3, bcd4: out std_logic_vector(3 downto 0)
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bcd0, bcd1: out std_logic_vector(3 downto 0)
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);
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end binary_bcd ;
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architecture behaviour of binary_bcd is
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type states is (start, shift, done);
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signal state, state_next: states;
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signal binary, binary_next: std_logic_vector(N-1 downto 0);
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signal bcds, bcds_reg, bcds_next: std_logic_vector(19 downto 0);
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-- output register keep output constant during conversion
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signal bcds_out_reg, bcds_out_reg_next: std_logic_vector(19 downto 0);
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-- need to keep track of shifts
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signal shift_counter, shift_counter_next: natural range 0 to N;
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begin
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process(clk, reset)
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begin
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if reset = '1' then
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binary <= (others => '0');
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bcds <= (others => '0');
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state <= start;
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bcds_out_reg <= (others => '0');
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shift_counter <= 0;
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elsif falling_edge(clk) then
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binary <= binary_next;
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bcds <= bcds_next;
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state <= state_next;
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bcds_out_reg <= bcds_out_reg_next;
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shift_counter <= shift_counter_next;
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end if;
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end process;
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convert:
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process(state, binary, binary_in, bcds, bcds_reg, shift_counter)
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begin
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state_next <= state;
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bcds_next <= bcds;
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binary_next <= binary;
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shift_counter_next <= shift_counter;
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case state is
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when start =>
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state_next <= shift;
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binary_next <= binary_in;
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bcds_next <= (others => '0');
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shift_counter_next <= 0;
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when shift =>
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if shift_counter = N then
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state_next <= done;
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else
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binary_next <= binary(N-2 downto 0) & 'L';
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bcds_next <= bcds_reg(18 downto 0) & binary(N-1);
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shift_counter_next <= shift_counter + 1;
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end if;
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when done =>
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state_next <= start;
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end case;
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end process;
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bcds_reg(19 downto 16) <= bcds(19 downto 16) + 3 when bcds(19 downto 16) > 4 else
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bcds(19 downto 16);
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bcds_reg(15 downto 12) <= bcds(15 downto 12) + 3 when bcds(15 downto 12) > 4 else
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bcds(15 downto 12);
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bcds_reg(11 downto 8) <= bcds(11 downto 8) + 3 when bcds(11 downto 8) > 4 else
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bcds(11 downto 8);
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bcds_reg(7 downto 4) <= bcds(7 downto 4) + 3 when bcds(7 downto 4) > 4 else
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bcds(7 downto 4);
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bcds_reg(3 downto 0) <= bcds(3 downto 0) + 3 when bcds(3 downto 0) > 4 else
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bcds(3 downto 0);
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bcds_out_reg_next <= bcds when state = done else
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bcds_out_reg;
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-- bcd4 <= bcds_out_reg(19 downto 16);
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-- bcd3 <= bcds_out_reg(15 downto 12);
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-- bcd2 <= bcds_out_reg(11 downto 8);
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bcd1 <= bcds_out_reg(7 downto 4);
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bcd0 <= bcds_out_reg(3 downto 0);
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end behaviour;

‎Lab7/clk_divider.vhd

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-- Engineer: Mehmet Cagri Aksoy
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity clk_converter is
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Port (
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clk_in : in STD_LOGIC;
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enable : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk_out: out STD_LOGIC
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);
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end clk_converter;
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architecture Behavioral of clk_converter is
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signal temporal: STD_LOGIC :='1';
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signal counter : integer range 0 to 100000000 := 0;
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begin
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process (enable,rst,clk_in,temporal,counter)
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begin
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if(rst='1') then
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temporal <= '1';
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counter <= 0;
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elsif (enable = '0') then
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temporal <= temporal;
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counter <= counter;
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elsif rising_edge(clk_in) then
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if (counter = 100000000) then
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temporal <= NOT(temporal);
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counter <= 0;
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else
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counter <= counter + 1;
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end if;
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end if;
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end process;
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clk_out <= temporal;
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end Behavioral;

‎Lab7/converter.vhd

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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity converter is
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Port (
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clk_in : in STD_LOGIC;
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enable : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk_out: out STD_LOGIC
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);
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end converter;
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architecture Behavioral of converter is
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signal temporal: STD_LOGIC :='1';
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signal counter : integer range 0 to 50000000 := 0;
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begin
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frequency_divider: process (enable,rst,clk_in,temporal,counter) begin
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if(rst='1') then
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temporal <= '1';
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counter <= 0;
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elsif (enable = '0') then
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temporal <= temporal;
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counter <= counter;
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elsif rising_edge(clk_in) then
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if (counter = 49999999) then
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temporal <= NOT(temporal);
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counter <= 0;
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else
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counter <= counter + 1;
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end if;
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end if;
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end process;
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clk_out <= temporal;
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end Behavioral;
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‎Lab7/seven_four.vhd

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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity seven_four is
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Port ( in1 : in STD_LOGIC_VECTOR (3 downto 0);
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in2 : in STD_LOGIC_VECTOR (3 downto 0);
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in3 : in STD_LOGIC_VECTOR (3 downto 0);
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in4 : in STD_LOGIC_VECTOR (3 downto 0);
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clk : in STD_LOGIC;
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dp : out STD_LOGIC;
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sel : out STD_LOGIC_VECTOR (3 downto 0);
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segment : out STD_LOGIC_VECTOR (6 downto 0)
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);
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end seven_four;
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architecture Behavioral of seven_four is
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signal counter : STD_LOGIC_VECTOR (17 downto 0);
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signal sev_in1, sev_in2, sev_in3, sev_in4 : STD_LOGIC_VECTOR (6 downto 0);
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begin
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dp <= '1';
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with in1 select
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sev_in1 (6 downto 0)<=
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"1000000" when "0000",
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"1111001" when "0001",
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"0100100" when "0010",
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"0110000" when "0011",
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"0011001" when "0100",
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"0010010" when "0101",
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"0000010" when "0110",
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"1111000" when "0111",
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"0000000" when "1000",
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"0010000" when "1001",
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"0001000" when "1010",
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"0000011" when "1011",
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"1000110" when "1100",
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"0100001" when "1101",
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"0000110" when "1110",
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"0001110" when "1111",
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"1111111" when others;
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with in2 select
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sev_in2 (6 downto 0)<=
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"1000000" when "0000",
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"1111001" when "0001",
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"0100100" when "0010",
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"0110000" when "0011",
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"0011001" when "0100",
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"0010010" when "0101",
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"0000010" when "0110",
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"1111000" when "0111",
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"0000000" when "1000",
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"0010000" when "1001",
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"0001000" when "1010",
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"0000011" when "1011",
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"1000110" when "1100",
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"0100001" when "1101",
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"0000110" when "1110",
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"0001110" when "1111",
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"1111111" when others;
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with in3 select
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sev_in3 (6 downto 0)<=
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"1000000" when "0000",
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"1111001" when "0001",
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"0100100" when "0010",
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"0110000" when "0011",
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"0011001" when "0100",
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"0010010" when "0101",
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"0000010" when "0110",
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"1111000" when "0111",
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"0000000" when "1000",
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"0010000" when "1001",
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"0001000" when "1010",
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"0000011" when "1011",
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"1000110" when "1100",
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"0100001" when "1101",
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"0000110" when "1110",
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"0001110" when "1111",
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"1111111" when others;
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with in4 select
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sev_in4 (6 downto 0)<=
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"1000000" when "0000",
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"1111001" when "0001",
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"0100100" when "0010",
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"0110000" when "0011",
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"0011001" when "0100",
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"0010010" when "0101",
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"0000010" when "0110",
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"1111000" when "0111",
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"0000000" when "1000",
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"0010000" when "1001",
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"0001000" when "1010",
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"0000011" when "1011",
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"1000110" when "1100",
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"0100001" when "1101",
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"0000110" when "1110",
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"0001110" when "1111",
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"1111111" when others;
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process (clk, sev_in1, sev_in2, sev_in3, sev_in4)
114+
variable sec : STD_LOGIC_VECTOR (1 downto 0) := "00" ;
115+
begin
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if(clk'event and clk = '1') then
117+
counter <= counter + 1;
118+
sec := (counter(17) & counter(16));
119+
end if;
120+
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case (sec) is
122+
when "00" =>
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sel <= "1110";
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segment <= sev_in1;
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when "01" =>
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sel <= "1101";
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segment <= sev_in2;
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when "10" =>
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sel <= "1011";
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segment <= sev_in3;
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when "11" =>
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sel <= "0111";
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segment <= sev_in4;
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when others =>
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sel <= "1111";
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segment <= "1111111";
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end case;
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end process;
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end Behavioral;
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‎Lab7/top.ucf

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NET "clk100Mhz" LOC = E3 | IOSTANDARD = LVCMOS33;
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NET "enable" LOC=J15 | IOSTANDARD=LVCMOS33;
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NET "DATA" LOC=L16 | IOSTANDARD=LVCMOS33;
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NET "reset" LOC=M13 | IOSTANDARD=LVCMOS33;
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NET "ledo<0>" LOC=H17 | IOSTANDARD=LVCMOS33;
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NET "ledo<1>" LOC=K15 | IOSTANDARD=LVCMOS33;
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NET "ledo<2>" LOC=J13 | IOSTANDARD=LVCMOS33;
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NET "ledo<3>" LOC=N14 | IOSTANDARD=LVCMOS33;
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NET "ledo<4>" LOC=R18 | IOSTANDARD=LVCMOS33;
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NET "ledo<5>" LOC=V17 | IOSTANDARD=LVCMOS33;
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NET "ledo<6>" LOC=U17 | IOSTANDARD=LVCMOS33;
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NET "ledo<7>" LOC=U16 | IOSTANDARD=LVCMOS33;
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NET "seg_out<0>" LOC=H15 | IOSTANDARD=LVCMOS33;
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NET "seg_out<1>" LOC=T10 | IOSTANDARD=LVCMOS33;
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NET "seg_out<2>" LOC=R10 | IOSTANDARD=LVCMOS33;
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NET "seg_out<3>" LOC=K16 | IOSTANDARD=LVCMOS33;
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NET "seg_out<4>" LOC=K13 | IOSTANDARD=LVCMOS33;
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NET "seg_out<5>" LOC=P15 | IOSTANDARD=LVCMOS33;
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NET "seg_out<6>" LOC=T11 | IOSTANDARD=LVCMOS33;
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NET "seg_out<7>" LOC=L18 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<0>" LOC=J17 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<1>" LOC=J18 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<2>" LOC=T9 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<3>" LOC=J14 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<4>" LOC=P14 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<5>" LOC=T14 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<6>" LOC=K2 | IOSTANDARD=LVCMOS33;
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NET "seg_sel<7>" LOC=U13 | IOSTANDARD=LVCMOS33;
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