Skip to content

Commit 829252b

Browse files
author
Organick
authored
Add files via upload
Vending Machine
1 parent 2976b1b commit 829252b

File tree

5 files changed

+360
-0
lines changed

5 files changed

+360
-0
lines changed

‎Lab8/EEM334-LAB8.pdf

207 KB
Binary file not shown.

‎Lab8/FSM.vhd

+115
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
library IEEE;
2+
use IEEE.STD_LOGIC_1164.ALL;
3+
use IEEE.NUMERIC_STD.ALL;
4+
--use IEEE.STD_LOGIC_ARITH.ALL;
5+
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
6+
7+
8+
entity FSM is
9+
Port ( item_select : in STD_LOGIC_VECTOR (1 downto 0);
10+
request : in STD_LOGIC;
11+
one_tl : in STD_LOGIC;
12+
take_item : in STD_LOGIC;
13+
reset : in STD_LOGIC;
14+
clk : in STD_LOGIC;
15+
ready_led : out STD_LOGIC;
16+
current_state : out STD_LOGIC_VECTOR(3 downto 0);
17+
girilen_para_out : out STD_LOGIC_VECTOR(3 downto 0));
18+
end FSM;
19+
20+
architecture Behavioral of FSM is
21+
22+
type state_type is (s0, s1, s2);
23+
24+
signal state_reg, state_next : state_type;
25+
signal istenen_urun_kaydi : std_logic_vector(1 downto 0);
26+
signal cash_increase : std_logic := '0';
27+
signal girilen_para : unsigned(3 downto 0) := "0000";
28+
signal count : unsigned (31 downto 0) := (others => '0');
29+
30+
begin
31+
32+
-- first process --
33+
process (state_reg, clk, reset)
34+
begin
35+
if (reset = '1') then
36+
state_reg <= s0;
37+
elsif (clk = '1' and clk'event) then
38+
state_reg <= state_next;
39+
end if;
40+
end process;
41+
42+
process (state_reg, take_item, request, item_select, one_tl)
43+
begin
44+
if (clk = '1' and clk'event) then
45+
case state_reg is
46+
when s0 =>
47+
ready_led <= '0';
48+
cash_increase <= '0';
49+
girilen_para <= "0000";
50+
if (request = '1') then
51+
istenen_urun_kaydi <= item_select;
52+
state_next <= s1;
53+
else
54+
state_next <= state_reg;
55+
end if;
56+
when s1 =>
57+
-- burada kullaniciya vakit taniyoruz !! --
58+
if (count < 250000000) then
59+
count <= count + 1;
60+
61+
girilen_para_out <= std_logic_vector(girilen_para);
62+
63+
if (cash_increase = '0' and one_tl = '1') then
64+
cash_increase <= '1';
65+
girilen_para <= girilen_para +1;
66+
elsif (one_tl = '0') then
67+
cash_increase <= '0';
68+
end if;
69+
else
70+
count <= (others => '0');
71+
girilen_para <= "0000";
72+
73+
if (item_select = "00" and (girilen_para = 1 or girilen_para > 1)) then
74+
istenen_urun_kaydi <= "00";
75+
state_next <= s2;
76+
elsif (item_select = "01" and (girilen_para = 2 or girilen_para > 2)) then
77+
istenen_urun_kaydi <= "01";
78+
state_next <= s2;
79+
elsif (item_select = "10" and (girilen_para = 3 or girilen_para > 3)) then
80+
istenen_urun_kaydi <= "10";
81+
state_next <= s2;
82+
elsif (item_select = "11" and (girilen_para = 4 or girilen_para > 4)) then
83+
istenen_urun_kaydi <= "11";
84+
state_next <= s2;
85+
else
86+
state_next <= s0;
87+
end if;
88+
end if;
89+
90+
when s2 =>
91+
ready_led <= '1';
92+
if (take_item = '1') then
93+
state_next <= s0;
94+
end if;
95+
end case;
96+
97+
end if;
98+
end process;
99+
100+
-- 7 segment
101+
process (state_reg)
102+
103+
begin
104+
105+
if (state_reg = s0) then
106+
current_state <= "0000";
107+
elsif (state_reg = s1) then
108+
current_state <= "0001";
109+
elsif (state_reg = s2) then
110+
current_state <= "0010";
111+
end if;
112+
113+
end process;
114+
115+
end Behavioral;

‎Lab8/seven_four.vhd

+146
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
2+
library IEEE;
3+
use IEEE.STD_LOGIC_1164.ALL;
4+
use IEEE.STD_LOGIC_ARITH.ALL;
5+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
6+
7+
entity seven_four is
8+
Port ( in1 : in STD_LOGIC_VECTOR (3 downto 0);
9+
in2 : in STD_LOGIC_VECTOR (3 downto 0);
10+
in3 : in STD_LOGIC_VECTOR (3 downto 0);
11+
in4 : in STD_LOGIC_VECTOR (3 downto 0);
12+
clk : in STD_LOGIC;
13+
dp : out STD_LOGIC;
14+
sel : out STD_LOGIC_VECTOR (3 downto 0);
15+
segment : out STD_LOGIC_VECTOR (6 downto 0)
16+
);
17+
end seven_four;
18+
19+
architecture Behavioral of seven_four is
20+
21+
signal counter : STD_LOGIC_VECTOR (17 downto 0);
22+
signal sev_in1, sev_in2, sev_in3, sev_in4 : STD_LOGIC_VECTOR (6 downto 0);
23+
24+
begin
25+
26+
dp <= '1';
27+
28+
with in1 select
29+
sev_in1 (6 downto 0)<=
30+
"1000000" when "0000",
31+
"1111001" when "0001",
32+
"0100100" when "0010",
33+
"0110000" when "0011",
34+
"0011001" when "0100",
35+
"0010010" when "0101",
36+
"0000010" when "0110",
37+
"1111000" when "0111",
38+
"0000000" when "1000",
39+
"0010000" when "1001",
40+
"0001000" when "1010",
41+
"0000011" when "1011",
42+
"1000110" when "1100",
43+
"0100001" when "1101",
44+
"0000110" when "1110",
45+
"0001110" when "1111",
46+
"1111111" when others;
47+
48+
with in2 select
49+
sev_in2 (6 downto 0)<=
50+
"1000000" when "0000",
51+
"1111001" when "0001",
52+
"0100100" when "0010",
53+
"0110000" when "0011",
54+
"0011001" when "0100",
55+
"0010010" when "0101",
56+
"0000010" when "0110",
57+
"1111000" when "0111",
58+
"0000000" when "1000",
59+
"0010000" when "1001",
60+
"0001000" when "1010",
61+
"0000011" when "1011",
62+
"1000110" when "1100",
63+
"0100001" when "1101",
64+
"0000110" when "1110",
65+
"0001110" when "1111",
66+
"1111111" when others;
67+
68+
69+
with in3 select
70+
sev_in3 (6 downto 0)<=
71+
"1000000" when "0000",
72+
"1111001" when "0001",
73+
"0100100" when "0010",
74+
"0110000" when "0011",
75+
"0011001" when "0100",
76+
"0010010" when "0101",
77+
"0000010" when "0110",
78+
"1111000" when "0111",
79+
"0000000" when "1000",
80+
"0010000" when "1001",
81+
"0001000" when "1010",
82+
"0000011" when "1011",
83+
"1000110" when "1100",
84+
"0100001" when "1101",
85+
"0000110" when "1110",
86+
"0001110" when "1111",
87+
"1111111" when others;
88+
89+
90+
with in4 select
91+
sev_in4 (6 downto 0)<=
92+
"1000000" when "0000",
93+
"1111001" when "0001",
94+
"0100100" when "0010",
95+
"0110000" when "0011",
96+
"0011001" when "0100",
97+
"0010010" when "0101",
98+
"0000010" when "0110",
99+
"1111000" when "0111",
100+
"0000000" when "1000",
101+
"0010000" when "1001",
102+
"0001000" when "1010",
103+
"0000011" when "1011",
104+
"1000110" when "1100",
105+
"0100001" when "1101",
106+
"0000110" when "1110",
107+
"0001110" when "1111",
108+
"1111111" when others;
109+
110+
111+
112+
113+
process (clk, sev_in1, sev_in2, sev_in3, sev_in4)
114+
variable sec : STD_LOGIC_VECTOR (1 downto 0) := "00" ;
115+
begin
116+
if(clk'event and clk = '1') then
117+
counter <= counter + 1;
118+
sec := (counter(17) & counter(16));
119+
end if;
120+
121+
case (sec) is
122+
when "00" =>
123+
sel <= "1110";
124+
segment <= sev_in1;
125+
126+
when "01" =>
127+
sel <= "1101";
128+
segment <= sev_in2;
129+
130+
when "10" =>
131+
sel <= "1011";
132+
segment <= sev_in3;
133+
134+
when "11" =>
135+
sel <= "0111";
136+
segment <= sev_in4;
137+
138+
when others =>
139+
sel <= "1111";
140+
segment <= "1111111";
141+
142+
end case;
143+
144+
end process;
145+
146+
end Behavioral;

‎Lab8/top.ucf

+37
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
#PACE: Start of Constraints generated by PACE
2+
3+
#PACE: Start of PACE I/O Pin Assignments
4+
5+
NET "clk" LOC = E3 | IOSTANDARD = LVCMOS33;
6+
NET "item_select<0>" LOC=J15 | IOSTANDARD=LVCMOS33;
7+
NET "item_select<1>" LOC=L16 | IOSTANDARD=LVCMOS33;
8+
9+
NET "request" LOC=P17 | IOSTANDARD=LVCMOS33;
10+
NET "one_tl" LOC=N17 | IOSTANDARD=LVCMOS33;
11+
NET "take_item" LOC=M17 | IOSTANDARD=LVCMOS33;
12+
NET "reset" LOC=M18 | IOSTANDARD=LVCMOS33;
13+
NET "ready_led" LOC=H17 | IOSTANDARD=LVCMOS33;
14+
15+
NET "seg_out<0>" LOC=H15 | IOSTANDARD=LVCMOS33;
16+
NET "seg_out<1>" LOC=T10 | IOSTANDARD=LVCMOS33;
17+
NET "seg_out<2>" LOC=R10 | IOSTANDARD=LVCMOS33;
18+
NET "seg_out<3>" LOC=K16 | IOSTANDARD=LVCMOS33;
19+
NET "seg_out<4>" LOC=K13 | IOSTANDARD=LVCMOS33;
20+
NET "seg_out<5>" LOC=P15 | IOSTANDARD=LVCMOS33;
21+
NET "seg_out<6>" LOC=T11 | IOSTANDARD=LVCMOS33;
22+
NET "seg_out<7>" LOC=L18 | IOSTANDARD=LVCMOS33;
23+
NET "seg_sel<0>" LOC=J17 | IOSTANDARD=LVCMOS33;
24+
NET "seg_sel<1>" LOC=J18 | IOSTANDARD=LVCMOS33;
25+
NET "seg_sel<2>" LOC=T9 | IOSTANDARD=LVCMOS33;
26+
NET "seg_sel<3>" LOC=J14 | IOSTANDARD=LVCMOS33;
27+
NET "seg_sel<4>" LOC=P14 | IOSTANDARD=LVCMOS33;
28+
NET "seg_sel<5>" LOC=T14 | IOSTANDARD=LVCMOS33;
29+
NET "seg_sel<6>" LOC=K2 | IOSTANDARD=LVCMOS33;
30+
NET "seg_sel<7>" LOC=U13 | IOSTANDARD=LVCMOS33;
31+
32+
33+
#PACE: Start of PACE Area Constraints
34+
35+
#PACE: Start of PACE Prohibit Constraints
36+
37+
#PACE: End of Constraints generated by PACE

‎Lab8/top.vhd

+62
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
library IEEE;
2+
use IEEE.STD_LOGIC_1164.ALL;
3+
use IEEE.NUMERIC_STD.ALL;
4+
use IEEE.STD_LOGIC_ARITH.ALL;
5+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
6+
7+
entity top is
8+
Port ( item_select : in STD_LOGIC_VECTOR (1 downto 0);
9+
request : in STD_LOGIC;
10+
one_tl : in STD_LOGIC;
11+
take_item : in STD_LOGIC;
12+
reset : in STD_LOGIC;
13+
clk : in STD_LOGIC;
14+
ready_led : out STD_LOGIC;
15+
seg_out : out STD_LOGIC_VECTOR (7 downto 0);
16+
seg_sel : out STD_LOGIC_VECTOR (7 downto 0)
17+
);
18+
end top;
19+
20+
architecture Behavioral of top is
21+
22+
component seven_four
23+
Port ( in1 : in STD_LOGIC_VECTOR (3 downto 0);
24+
in2 : in STD_LOGIC_VECTOR (3 downto 0);
25+
in3 : in STD_LOGIC_VECTOR (3 downto 0);
26+
in4 : in STD_LOGIC_VECTOR (3 downto 0);
27+
clk : in STD_LOGIC;
28+
dp : out STD_LOGIC;
29+
sel : out STD_LOGIC_VECTOR (3 downto 0);
30+
segment : out STD_LOGIC_VECTOR (6 downto 0)
31+
);
32+
end component;
33+
34+
component FSM
35+
Port ( item_select : in STD_LOGIC_VECTOR (1 downto 0);
36+
request : in STD_LOGIC;
37+
one_tl : in STD_LOGIC;
38+
take_item : in STD_LOGIC;
39+
reset : in STD_LOGIC;
40+
clk : in STD_LOGIC;
41+
ready_led : out STD_LOGIC;
42+
current_state : out STD_LOGIC_VECTOR(3 downto 0);
43+
girilen_para_out : out STD_LOGIC_VECTOR(3 downto 0)
44+
);
45+
end component;
46+
47+
signal current_state_out : STD_LOGIC_VECTOR(3 downto 0);
48+
signal w4 : STD_LOGIC;
49+
signal w5 : STD_LOGIC_VECTOR (6 downto 0);
50+
signal seg_sel_4 : STD_LOGIC_VECTOR (3 downto 0);
51+
signal show_TL : STD_LOGIC_VECTOR (3 downto 0);
52+
53+
54+
begin
55+
56+
c0 : FSM port map(item_select, request, one_tl, take_item, reset, clk, ready_led, current_state_out, show_TL);
57+
c1 : seven_four port map (show_TL, "0000", current_state_out, "0101", clk , w4, seg_sel_4, w5);
58+
59+
seg_out <= (w5 & w4);
60+
seg_sel <= "1111" & seg_sel_4;
61+
62+
end Behavioral;

0 commit comments

Comments
 (0)