Skip to content

Commit eb72143

Browse files
pConstpConst
committed
README update
1 parent 3aa5679 commit eb72143

File tree

1 file changed

+57
-57
lines changed

1 file changed

+57
-57
lines changed

‎README.md

Lines changed: 57 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ For your convinience I`ve tagged some sources by their "difficulty":
2626
If you are a beginner in HW design - you may want to start exploring :green_circle: code first.
2727
Almost every source file in the repository contains detailed description and instantiation template!
2828

29-
| USAGE | DIRECTORY | DESCRIPTION |
29+
| | DIRECTORY | DESCRIPTION |
3030
|---------------|--------------|-------------|
3131
| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
3232
| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources |
@@ -43,64 +43,64 @@ Almost every source file in the repository contains detailed description and ins
4343
| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS |
4444
| | xpm | Xilinx parametrizable macros sources |
4545

46-
| USAGE | FILE | DESCRIPTION |
47-
|----------------|--------------------|-------------|
48-
| | adder_tree.sv | adding multiple values together in parallel |
49-
| | axi4l_logger.sv | |
50-
| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
51-
| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
52-
| | cdc_data.sv | |
53-
| | cdc_strobe.sv | |
54-
| :green_circle: | clk_divider.sv | wide reference clock divider |
55-
| | clogb2.svh | |
56-
| :green_circle: | debounce.v | two-cycle debounce for input buttons |
57-
| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
58-
| | delayed_event.sv | |
59-
| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
60-
| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
61-
| | encoder.v | digital encoder input logic module |
62-
| :red_circle: | fast_counter.sv | |
63-
| | fifo_combiner.sv | |
64-
| | fifo_operator.sv | |
46+
| | FILE | DESCRIPTION |
47+
|----------------|-------------------- |-------------|
48+
| | adder_tree.sv | adding multiple values together in parallel |
49+
| | axi4l_logger.sv | sniffs all AXI transactions and stores address and data to fifo |
50+
| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
51+
| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
52+
| | cdc_data.sv | standard two-stage data synchronizer |
53+
| | cdc_strobe.sv | clock crossing synchronizer for one-cycle strobes |
54+
| :green_circle: | clk_divider.sv | wide reference clock divider |
55+
| | clogb2.svh | calculates counter/address width based on specified vector/RAM depth |
56+
| :green_circle: | debounce.v | two-cycle debounce for input buttons |
57+
| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
58+
| | delayed_event.sv | generates delayed pulse one clock width |
59+
| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
60+
| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
61+
| | encoder.v | digital encoder input logic module |
62+
| :red_circle: | fast_counter.sv | synthetic counter |
63+
| | fifo_combiner.sv | accumulates data words from multiple FIFOs to a single output FIFO |
64+
| | fifo_operator.sv | performs custom operation on data words from multiple FIFOs and stores result to a single output FIFO |
6565
| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation |
6666
| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
67-
| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
68-
| :red_circle: | gray_functions.vh | |
69-
| :green_circle: | hex2ascii.sv | |
70-
| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
71-
| | lifo.sv | single-clock LIFO buffer (stack) implementation |
72-
| | main_tb.sv | basic testbench template |
73-
| | moving_average.sv | |
74-
| | pack_unpack_array.v | |
75-
| | pattern_detect.sv | |
76-
| | pdm_modulator.sv | |
77-
| | pos2bin.sv | converts positional (one-hot) value to binary representation |
78-
| | prbs_gen_chk.sv | PRBS pattern generator or checker |
79-
| | preview_fifo.sv | |
80-
| | priority_enc.sv | |
81-
| | pulse_gen.sv | generates pulses with given width and delay |
82-
| | pulse_stretch.sv | configurable pulse stretcher/extender module |
83-
| | pwm_modulator.sv | |
84-
| :red_circle: | read_ahead_buf.sv | |
85-
| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
86-
| | reset_set_comb.sv | |
87-
| | reverse_bytes.sv | reverses bytes order within multi-byte array |
88-
| | reverse_dimensions.sv | |
89-
| | reverse_vector.sv | reverses signal order within multi-bit bus |
90-
| | round_robin_enc.sv | |
91-
| | round_robin_performance_enc.sv | |
92-
| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
93-
| | set_reset_comb.sv | |
94-
| | sim_clk_gen.sv | |
95-
| :red_circle: | soft_latch.sv | |
96-
| | spi_master.sv | universal spi master module |
97-
| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | |
98-
| :red_circle: | true_single_port_write_first_ram.sv | |
99-
| | uart_debug_printer.sv | |
100-
| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
101-
| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
102-
| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
103-
| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
67+
| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
68+
| :red_circle: | gray_functions.vh | Gray code parametrizable converter functions |
69+
| :green_circle: | hex2ascii.sv | converts 4-bit binary nibble to 8-bit human-readable ASCII char |
70+
| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
71+
| | lifo.sv | single-clock LIFO buffer (stack) implementation |
72+
| | main_tb.sv | basic testbench template |
73+
| | moving_average.sv | Simple moving average implementation |
74+
| | pack_unpack_array.v | macros for packing and unpacking 2D and 3D vectors in Verilog-2001 |
75+
| | pattern_detect.sv | detects data pattern specified |
76+
| | pdm_modulator.sv | pulse density modulation generator module |
77+
| | pos2bin.sv | converts positional (one-hot) value to binary representation |
78+
| | prbs_gen_chk.sv | PRBS pattern generator or checker |
79+
| | preview_fifo.sv | FIFO with an ability to be read 0, 1 or 2 words at once |
80+
| | priority_enc.sv | combinational priority_encoder |
81+
| | pulse_gen.sv | generates pulses with given width and delay |
82+
| | pulse_stretch.sv | configurable pulse stretcher/extender module |
83+
| | pwm_modulator.sv | pulse width modulation generator |
84+
| :red_circle: | read_ahead_buf.sv | substitutes fifo read port and performs fifo data update at the same clock cycle |
85+
| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
86+
| | reset_set_comb.sv | synchronous SR trigger, but has a combinational output |
87+
| | reverse_bytes.sv | reverses bytes order within multi-byte array |
88+
| | reverse_dimensions.sv | reverses dimension order in SystemVerilog 2D vector |
89+
| | reverse_vector.sv | reverses signal order within multi-bit bus |
90+
| | round_robin_enc.sv | round robin combinational encoder |
91+
| | round_robin_performance_enc.sv | performance improved round robin encoder |
92+
| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
93+
| | set_reset_comb.sv | synchronous SR trigger, but has a combinational output |
94+
| | sim_clk_gen.sv | testbench clock generator |
95+
| :red_circle: | soft_latch.sv | combinational data hold circuit |
96+
| | spi_master.sv | universal spi master module |
97+
| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | double port RAM/ROM module |
98+
| :red_circle: | true_single_port_write_first_ram.sv | single port RAM/ROM module |
99+
| | uart_debug_printer.sv | debug data printer to UART terminal |
100+
| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
101+
| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
102+
| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
103+
| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
104104

105105
Also added testbenches for selected modules.
106106

0 commit comments

Comments
 (0)