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accelerator.v

+80
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
`timescale 1ns / 1ps
2+
`define FIXED_POINT 1
3+
module acclerator #(
4+
parameter n = 9'h00a, //size of the input image/activation map
5+
parameter k = 9'h003, //size of the convolution window
6+
parameter p = 9'h002, //size of the pooling window
7+
parameter s = 1, //stride value during convolution
8+
parameter ptype = 1, //0 => average pooling , 1 => max_pooling
9+
parameter act_type = 0,//0 => ReLu activation function, 1=> Hyperbolic tangent activation function
10+
parameter N = 16, //Bit width of activations and weights (total datapath width)
11+
parameter Q = 12, //Number of fractional bits in case of fixed point representation
12+
parameter AW = 10, //Needed in case of tanh activation function to set the size or ROM
13+
parameter DW = 16, //Datapath width = N
14+
parameter p_sqr_inv = 16'b0000010000000000 // = 1/p**2 in the (N,Q) format being used currently
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)(
16+
input clk,
17+
input global_rst,
18+
input ce,
19+
input [15:0] activation,
20+
input [(k*k)*16-1:0] weight1,
21+
output [15:0] data_out,
22+
output valid_op,
23+
output end_op,
24+
output [15:0] conv_out,
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output conv_valid,
26+
output conv_end
27+
);
28+
29+
wire [N-1:0] conv_op;
30+
wire valid_conv,end_conv;
31+
wire valid_ip;
32+
wire [N-1:0] relu_op;
33+
wire [N-1:0] tanh_op;
34+
wire [N-1:0] pooler_ip;
35+
wire [N-1:0] pooler_op;
36+
reg [N-1:0] pooler_op_reg;
37+
38+
convolver #(.n(n),.k(k),.s(s),.N(N),.Q(Q)) conv(//Convolution engine
39+
.clk(clk),
40+
.ce(ce),
41+
.weight1(weight1),
42+
.global_rst(global_rst),
43+
.activation(activation),
44+
.conv_op(conv_op),
45+
.end_conv(end_conv),
46+
.valid_conv(valid_conv)
47+
);
48+
assign conv_valid = valid_conv;
49+
assign conv_end = end_conv;
50+
assign conv_out = conv_op;
51+
52+
assign valid_ip = valid_conv && (!end_conv);
53+
54+
relu #(.N(N)) act( // ReLu Activation function
55+
.din_relu(conv_op),
56+
.dout_relu(relu_op)
57+
);
58+
59+
tanh_lut #(.AW(AW),.DW(DW),.N(N),.Q(Q)) tanh( //Hyperbolic Tangent Activation function
60+
.clk(clk),
61+
.rst(global_rst),
62+
.phase(conv_op),
63+
.tanh(tanh_op)
64+
);
65+
66+
assign pooler_ip = act_type ? tanh_op : relu_op; //alternatively you could use macros to save resources when using ReLu
67+
68+
pooler #(.N(N),.Q(Q),.m(n-k+1),.p(p),.ptype(ptype),.p_sqr_inv(p_sqr_inv)) pool( //Pooling Unit
69+
.clk(clk),
70+
.ce(valid_ip),
71+
.master_rst(global_rst),
72+
.data_in(pooler_ip),
73+
.data_out(pooler_op),
74+
.valid_op(valid_op),
75+
.end_op(end_op)
76+
);
77+
78+
assign data_out = pooler_op;
79+
80+
endmodule

accelerator_tb.v

+86
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
`timescale 1ns / 1ps
2+
`define FIXED_POINT 1
3+
module accelerator_tb;
4+
5+
// Inputs
6+
reg clk;
7+
reg ce;
8+
reg [143:0] weight1;
9+
reg global_rst;
10+
reg [15:0] activation;
11+
12+
// Outputs
13+
wire [15:0] acc_op,conv_out;
14+
wire conv_valid,conv_end;
15+
wire end_op;
16+
wire valid_op;
17+
integer i;
18+
parameter clkp = 20;
19+
integer ip_file,r3,op_file;
20+
// Instantiate the Unit Under Test (UUT)
21+
acclerator #(.n('d6),.p('d2),.k('d3),.N('d16),.Q('d12),.ptype('d0),.s('d1),.psqr_inv(16'b0000010000000000)) uut (
22+
.clk(clk),
23+
.ce(ce),
24+
.weight1(weight1),
25+
.global_rst(global_rst),
26+
.activation(activation),
27+
.data_out(acc_op),
28+
.valid_op(valid_op),
29+
.end_op(end_op),
30+
.conv_out(conv_out),
31+
.conv_valid(conv_valid),
32+
.conv_end(conv_end)
33+
);
34+
35+
initial begin
36+
// Initialize Inputs
37+
clk = 0;
38+
ce = 0;
39+
weight1 = 0;
40+
global_rst = 0;
41+
activation = 0;
42+
43+
// Wait 100 ns for global reset to finish
44+
#100;
45+
46+
clk = 0;
47+
ce = 0;
48+
weight1 = 0;
49+
activation = 0;
50+
global_rst =1;
51+
#60;
52+
global_rst =0;
53+
//#10;
54+
ce=1;
55+
ip_file = $fopen("activations.txt","r");
56+
op_file = $fopen("acc_out.txt","a");
57+
`ifdef FIXED_POINT
58+
weight1 = 144'b1111100110010111_0000001111010001_1111011010001101_1111101010010011_1111110101110100_1111110111101111_0000000110010110_1111000011010101_1111110111110100;
59+
`else
60+
weight1 = 144'h0008_0007_0006_0005_0004_0003_0002_0001_0000;
61+
`endif
62+
// Initialize Inputs
63+
for(i=0;i<36;i=i+1) begin
64+
`ifdef FIXED_POINT
65+
r3 = $fscanf(ip_file,"%b\n",activation);
66+
`else
67+
activation = i;
68+
`endif
69+
#clkp;
70+
end
71+
end
72+
always #(clkp/2) clk = ~clk;
73+
74+
always@(posedge clk) begin
75+
if(valid_op & !end_op) begin
76+
$fdisplay(op_file,"%b",acc_op);
77+
end
78+
if(conv_end) begin
79+
if(ce)
80+
begin
81+
$fdisplay(op_file,"%s%0d","end",0);
82+
$finish;
83+
end
84+
end
85+
end
86+
endmodule

comparator2.v

+47-8
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,48 @@
1-
`timescale 1ns / 1ps
2-
3-
module comparator2(
4-
input [31:0] ip1,
5-
input [31:0] ip2,
6-
output [31:0] comp_op);
7-
8-
assign comp_op = (ip1>ip2) ? ip1:ip2;
1+
`timescale 1ns / 1ps
2+
3+
module comparator2 #(
4+
parameter N = 16,
5+
parameter Q = 12,
6+
parameter ptype = 1
7+
)(
8+
input ce,
9+
input [N-1:0] ip1,
10+
input [N-1:0] ip2,
11+
output [N-1:0] comp_op
12+
);
13+
14+
wire [N-1:0] ip1_2cmp, ip2_2cmp; //two's complemented versions of the input values
15+
reg [N-1:0] temp;
16+
17+
18+
assign ip1_2cmp = {~ip1[N-1],~ip1[N-2:0] + 1'b1};
19+
assign ip2_2cmp = {~ip2[N-1],~ip2[N-2:0] + 1'b1};
20+
assign comp_op = ce ? temp : 'd0;
21+
//assign comp_op = ptype ? (ip1 + ip2) : ((ip1>ip2) ? ip1:ip2);
22+
always@(*)
23+
begin
24+
if(ptype == 0)
25+
begin
26+
temp = ip1 + ip2; //when in the average pooling mode, the comparator doubles up as the adder
27+
end
28+
else
29+
begin
30+
if( (ip1[N-1] == 0) & (ip2[N-1] == 0) )
31+
begin
32+
temp = (ip1>ip2) ? ip1:ip2;
33+
end
34+
else if ( (ip1[N-1] == 1) & (ip2[N-1] == 1) )
35+
begin
36+
temp = (ip1_2cmp > ip2_2cmp) ? ip2 : ip1; //higher the magnitude of a -ve no. lower its value
37+
end
38+
else if ( (ip1[N-1] == 1) & (ip2[N-1] == 0) )
39+
begin
40+
temp = ip2;
41+
end
42+
else if ( (ip1[N-1] == 0) & (ip2[N-1] == 1) )
43+
begin
44+
temp = ip1;
45+
end
46+
end
47+
end
948
endmodule

control_logic2.v

+38-24
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,20 @@
11
`timescale 1ns / 1ps
22

3+
//1. normal case : just store the max value in the register.
4+
//2. end of one neighbourhood: store the max value to the shift register.
5+
//3. end of row: store the max value in the shift register and then load the max register from the shift register.
6+
//4. end of neighbourhood in the last row: make output valid and store the max value in the max register.
7+
//5. end of last neighbourhood of last row: make op valid and store the max value in the max register and then reset the entire module.
38

4-
control_logic2(
9+
//SIGNALS TO BE HANDLED IN EACH CASE
10+
//CASE 1 2 3 4 5
11+
//1. load _sr low high high high low
12+
//2. sel low low high high low
13+
//3. rst_m low high low low low
14+
//4. op_en low low low high high
15+
//5. global_rst low low low low high
16+
17+
module control_logic2(
518
input clk,
619
input master_rst,
720
input ce,
@@ -30,7 +43,7 @@ control_logic2(
3043
end_op <=0;
3144
end
3245
else begin
33-
if(((col_count+1)%p !=0)&&(row_count == p-1)&&(col_count == p*count+ (p-2))&&ce)
46+
if(((col_count+1)%p !=0)&&(row_count == p-1)&&(col_count == p*count + (p-2))&&ce) //op_en
3447
begin
3548
op_en <=1;
3649
end
@@ -39,29 +52,30 @@ control_logic2(
3952
end
4053
if(ce)
4154
begin
42-
if(nbgh_row_count == m/p)
43-
begin
55+
if(nbgh_row_count == m/p) //end_op
56+
begin
4457
end_op <=1;
4558
end
4659
else
4760
begin
4861
end_op <=0;
4962
end
5063

51-
if(((col_count+1) % p != 0)&&(col_count == m-2)&&(row_count == p-1))
52-
begin
53-
global_rst <= 1;
54-
end
64+
if(((col_count+1) % p != 0)&&(col_count == m-2)&&(row_count == p-1)) //global_rst and pause_ip
65+
begin
66+
global_rst <= 1; // (reset everything)
67+
end
5568
else
5669
begin
5770
global_rst <= 0;
5871
end
5972

6073

6174

62-
63-
if((((col_count+1) % p == 0)&&(count != m/p-1)&&(row_count != p-1))||((col_count == m-1)&&(row_count == p-1)))
64-
begin
75+
//end
76+
77+
if((((col_count+1) % p == 0)&&(count != m/p-1)&&(row_count != p-1))||((col_count == m-1)&&(row_count == p-1))) //rst_m
78+
begin
6579
rst_m <= 1;
6680
end
6781
else
@@ -75,19 +89,19 @@ control_logic2(
7589
end
7690
else
7791
begin
78-
if((((col_count) % p == 0)&&(count == m/p-1)&&(row_count != p-1))|| (((col_count) % p == 0)&&(count != m/p-1)&&(row_count == p-1))) begin
79-
sel<=2'b01;
92+
if((((col_count) % p == 0)&&(count == m/p-1)&&(row_count != p-1))|| (((col_count) % p == 0)&&(count != m/p-1)&&(row_count == p-1))) begin //sel
93+
sel<=2'b01;
8094
end
8195
else
8296
begin
8397
sel <= 2'b00;
8498
end
8599
end
86100

87-
if((((col_count+1) % p == 0)&&((count == m/p-1)))||((col_count+1) % p == 0)&&((count != m/p-1)))
88-
begin
89-
load_sr <= 1;
90-
end
101+
if((((col_count+1) % p == 0)&&((count == m/p-1)))||((col_count+1) % p == 0)&&((count != m/p-1))) //load_sr
102+
begin
103+
load_sr <= 1; //&&(row_count!=p-1)
104+
end
91105
else
92106
begin
93107
load_sr <= 0;
@@ -96,8 +110,8 @@ control_logic2(
96110
end
97111
end
98112

99-
always@(posedge clk) begin
100-
if(master_rst) begin
113+
always@(posedge clk) begin //counters
114+
if(master_rst) begin
101115
row_count <=0;
102116
col_count <=32'hffffffff;
103117
count <=32'hffffffff;
@@ -110,14 +124,14 @@ control_logic2(
110124
if(global_rst)
111125
begin
112126
row_count <=0;
113-
col_count <=32'h0;
114-
count <=32'h0;
115-
nbgh_row_count <= nbgh_row_count + 1'b1;
127+
col_count <=32'h0;//ffffffff;
128+
count <=32'h0;//ffffffff;
129+
nbgh_row_count <= nbgh_row_count + 1'b1;
116130
end
117131
else
118132
begin
119-
if(((col_count+1) % p == 0)&&(count == m/p-1)&&(row_count != p-1))
120-
begin
133+
if(((col_count+1) % p == 0)&&(count == m/p-1)&&(row_count != p-1)) //col_count and row_count
134+
begin
121135
col_count <= 0;
122136
row_count <= row_count + 1'b1;
123137
count <=0;

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