extra state for STIDP ; but commented out, no difference, issue lies somewhere else

Author: varkenvarken

cpu.v

@@ -81,6 +81,7 @@ module cpu(
 	localparam RETURN5   = 5'd24; // next state is always FETCH
 	localparam WAITBASER = 5'd25; // next state is always WAITBASER1
 	localparam WAITBASER1= 5'd26; // next state is always FETCH
+	localparam STIDPWAIT = 5'd31; // next state is always FETCH
 	reg [4:0] state = START;
 
 	wire [4:0] rom_raddr, next_state;
@@ -184,7 +185,7 @@ module cpu(
 																c_waddr <= base1 + D;
 																write_en <= 1;
 																dwrite <= A;
-																state <= FETCH;
+																state <= FETCH; //STIDPWAIT; // FETCH
 																if(register==3)	D <= D + 1;
 															  end
 													default : state <= FETCH;
@@ -344,6 +345,7 @@ module cpu(
 								state <= FETCH;
 							end
 						end
+			//STIDPWAIT:	if(register==3)	D <= D + 1;
 		endcase
 	end
 

rom.py

@@ -99,6 +99,7 @@ def genrom(data):
 RETURN5   = 24; # next state is always FETCH
 WAITBASER = 25; # next state is always WAITBASER1
 WAITBASER1= 26; # next state is always FETCH
+STIDPWAIT = 31; # next state is always FETCH
 
 data = {
     START     :START,
@@ -127,7 +128,8 @@ def genrom(data):
     RETURN4   :RETURN5,
     RETURN5   :FETCH,
     WAITBASER :WAITBASER1,
-    WAITBASER1:FETCH
+    WAITBASER1:FETCH,
+    STIDPWAIT :FETCH,
     }
 
 data = [data[k] for k in sorted(data)]

rom.v

@@ -13,7 +13,7 @@ module rom32x4 (
 		.WRITE_MODE(1), 
 		.READ_MODE(1),
     .INIT_0(256'h0100000100540050000100450001004100400005001100110004000100140000),
-    .INIT_1(256'h0000000000000000000000010144000101400115011401110001010501040101),
+    .INIT_1(256'h0000000000000000000100010144000101400115011401110001010501040101),
     .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
     .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
     .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),