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Add OpenLane Support#53

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mu2519 wants to merge 16 commits intoPyHDI:developPyHDI/veriloggen:developfrom

mu2519:feature-asicmu2519/veriloggen:feature-asicCopy head branch name to clipboard

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Commits on Feb 15, 2023

• first ASIC support

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  289044c

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• Improved API for configuration generation

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• Added simulator and fixed bugs

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Commits on Feb 16, 2023

• Changed code for backward compatibility

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  76def28

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• Added one example for ASIC

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• Added rectpack to dependencies

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• Modified APIs

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Commits on Feb 20, 2023

• Modified the root conftest.py

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• Added .coveragerc

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• Added a test case for veriloggen.asic.sram

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• Modified pytest.ini, setup.py, and conftest.py to improve testing

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Commits on Feb 21, 2023

• Added a test case for a configuration file checker

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Commits on Mar 5, 2023

• Added a test case for matrix multiplication with ASIC

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  faa804d

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• Fixed a problem

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  b7f9c87

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Commits on Mar 25, 2023

• Merge branch 'PyHDI:develop' into feature-asic

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• Removed a meaningless file

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