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add version of trueDualPortBlockRam that sets the initial RAM contents #2204

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add version of trueDualPortBlockRam that sets the initial RAM contents #2204

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f2f0dd6
add version of trueDualPortBlockRam that sets the initial RAM contents
hydrolarus May 11, 2022
98f7cb1
apply doc suggestions from code review
hydrolarus May 12, 2022
8b0eca7
add changelog entry
hydrolarus May 12, 2022
86166dc
Test with initial contents.
lmbollen Jun 13, 2022
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67 changes: 65 additions & 2 deletions clash-lib/prims/systemverilog/Clash_Explicit_BlockRam.primitives.yaml
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,69 @@
, NFDataX a ~ARG[4]
) =>

Vec nAddrs a -> ~ARG[5]

Clock domA -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA Bool -> ~ARG[8]
Signal domA (Index nAddrs) -> ~ARG[9]
Signal domA a -> ~ARG[10]

Clock domB -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB Bool -> ~ARG[13]
Signal domB (Index nAddrs) -> ~ARG[14]
Signal domB a -> ~ARG[15]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// Shared memory
logic [~SIZE[~TYP[10]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

~SIGD[~GENSYM[data_slow][1]][10];
~SIGD[~GENSYM[data_fast][2]][15];

initial begin
~SYM[0] = ~CONST[5];
end

// Port A
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[6]) begin
if(~ARG[6]) begin
~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[9]]~THEN~ARG[9]~ELSE0~FI];
if(~ARG[8]) begin
~SYM[1] <= ~ARG[10];
~SYM[0][~IF~SIZE[~TYP[9]]~THEN~ARG[9]~ELSE0~FI] <= ~ARG[10];
end
end
end

// Port B
always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[11]) begin
if(~ARG[12]) begin
~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[14]]~THEN~ARG[14]~ELSE0~FI];
if(~ARG[13]) begin
~SYM[2] <= ~ARG[15];
~SYM[0][~IF~SIZE[~TYP[14]]~THEN~ARG[14]~ELSE0~FI] <= ~ARG[15];
end
end
end

assign ~RESULT = {~SYM[1], ~SYM[2]};
// end trueDualPortBlockRam
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRamU#
kind: Declaration
type: |-
trueDualPortBlockRamU# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Expand All @@ -157,7 +220,7 @@
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// trueDualPortBlockRamU begin
// Shared memory
logic [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

Expand Down Expand Up @@ -187,4 +250,4 @@
end

assign ~RESULT = {~SYM[1], ~SYM[2]};
// end trueDualPortBlockRam
// end trueDualPortBlockRamU
73 changes: 71 additions & 2 deletions clash-lib/prims/verilog/Clash_Explicit_BlockRam.primitives.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,75 @@
, NFDataX a ~ARG[4]
) =>

Vec nAddrs a -> ~ARG[5]

Clock domA -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA Bool -> ~ARG[8]
Signal domA (Index nAddrs) -> ~ARG[9]
Signal domA a -> ~ARG[10]

Clock domB -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB Bool -> ~ARG[13]
Signal domB (Index nAddrs) -> ~ARG[14]
Signal domB a -> ~ARG[15]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// Shared memory
reg [~SIZE[~TYP[10]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

reg ~SIGD[~GENSYM[data_slow][1]][10];
reg ~SIGD[~GENSYM[data_fast][2]][15];

reg ~TYP[5] ~GENSYM[ram_init][3];
integer ~GENSYM[i][4];
initial begin
~SYM[3] = ~CONST[5];
for (~SYM[4]=0; ~SYM[4] < ~LENGTH[~TYP[5]]; ~SYM[4] = ~SYM[4] + 1) begin
~SYM[1][~LENGTH[~TYP[5]]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYP[10]]+:~SIZE[~TYP[10]]];
end
end

// Port A
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[6]) begin
if(~ARG[7]) begin
~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[9]]~THEN~ARG[9]~ELSE0~FI];
if(~ARG[8]) begin
~SYM[1] <= ~ARG[10];
~SYM[0][~IF~SIZE[~TYP[9]]~THEN~ARG[9]~ELSE0~FI] <= ~ARG[10];
end
end
end

// Port B
always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[11]) begin
if(~ARG[12]) begin
~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[14]]~THEN~ARG[14]~ELSE0~FI];
if(~ARG[13]) begin
~SYM[2] <= ~ARG[15];
~SYM[0][~IF~SIZE[~TYP[14]]~THEN~ARG[14]~ELSE0~FI] <= ~ARG[15];
end
end
end

assign ~RESULT = {~SYM[1], ~SYM[2]};

// end trueDualPortBlockRam
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRamU#
kind: Declaration
type: |-
trueDualPortBlockRamU# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Expand All @@ -168,7 +237,7 @@
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// trueDualPortBlockRamU begin
// Shared memory
reg [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

Expand Down Expand Up @@ -199,4 +268,4 @@

assign ~RESULT = {~SYM[1], ~SYM[2]};

// end trueDualPortBlockRam
// end trueDualPortBlockRamU
70 changes: 68 additions & 2 deletions clash-lib/prims/vhdl/Clash_Explicit_BlockRam.primitives.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -181,6 +181,72 @@
, NFDataX a ~ARG[4]
) =>

Vec nAddrs a -> ~ARG[5]

Clock domA -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA Bool -> ~ARG[8]
Signal domA (Index nAddrs) -> ~ARG[9]
Signal domA a -> ~ARG[10]

Clock domB -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB Bool -> ~ARG[13]
Signal domB (Index nAddrs) -> ~ARG[14]
Signal domB a -> ~ARG[15]
(Signal domA a, Signal domB a)
template: |-
-- trueDualPortBlockRam begin
~GENSYM[~RESULT_trueDualPortBlockRam][1] : block
-- Shared memory
type mem_type is array ( ~LIT[1]-1 downto 0 ) of ~TYP[10];
shared variable mem : mem_type := ~CONST[5];
signal ~GENSYM[a_dout][2] : ~TYP[10];
signal ~GENSYM[b_dout][3] : ~TYP[15];
begin

-- Port A
process(~ARG[6])
begin
if(rising_edge(~ARG[6])) then
if(~ARG[7]) then
if(~ARG[8]) then
mem(~IF~SIZE[~TYP[9]]~THENto_integer(~ARG[9])~ELSE0~FI) := ~ARG[10];
end if;
~SYM[2] <= mem(~IF~SIZE[~TYP[9]]~THENto_integer(~ARG[9])~ELSE0~FI);
end if;
end if;
end process;

-- Port B
process(~ARG[11])
begin
if(rising_edge(~ARG[11])) then
if(~ARG[12]) then
if(~ARG[13]) then
mem(~IF~SIZE[~TYP[14]]~THENto_integer(~ARG[14])~ELSE0~FI) := ~ARG[15];
end if;
~SYM[3] <= mem(~IF~SIZE[~TYP[14]]~THENto_integer(~ARG[14])~ELSE0~FI);
end if;
end if;
end process;

~RESULT <= (~SYM[2], ~SYM[3]);
end block;
-- end trueDualPortBlockRam
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRamU#
kind: Declaration
type: |-
trueDualPortBlockRamU# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Expand All @@ -194,7 +260,7 @@
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
-- trueDualPortBlockRam begin
-- trueDualPortBlockRamU begin
~GENSYM[~RESULT_trueDualPortBlockRam][1] : block
-- Shared memory
type mem_type is array ( ~LIT[1]-1 downto 0 ) of ~TYP[9];
Expand Down Expand Up @@ -231,4 +297,4 @@

~RESULT <= (~SYM[2], ~SYM[3]);
end block;
-- end trueDualPortBlockRam
-- end trueDualPortBlockRamU
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