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*stm32:CMSIS:gpio, rcc - compatibiluty vs CMSIS library #58

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f4a4435
*stm32:CMSIS:gpio, rcc - compatibiluty vs CMSIS library provided. it …
alexrayne Nov 30, 2016
edd9f04
+ARMCC, CMSIS:cm_enable/disable_interrupts, cm_mask_interrupts - add …
alexrayne May 24, 2017
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7 changes: 7 additions & 0 deletions include/libopencmsis/core_cm3.h
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#ifndef OPENCMSIS_CORECM3_H
#define OPENCMSIS_CORECM3_H

#include <unicore-mx/common/cmsis.h>
#include <unicore-mx/cm3/common.h>
#include <unicore-mx/cm3/cortex.h>
#include <unicore-mx/cm3/memorymap.h>
Expand Down Expand Up @@ -88,6 +89,10 @@ static inline void NVIC_DisableIRQ(uint8_t irqn)

/* stubs for efm32_int */

//* looks like ARMCC have this by internals

#if __CMSIS_USE==0
#if defined ( __GNUC__ )
static inline void __enable_irq(void)
{
cm_enable_interrupts();
Expand All @@ -96,6 +101,8 @@ static inline void __disable_irq(void)
{
cm_disable_interrupts();
}
#endif //defined ( __GNUC__ )
#endif // __CMSIS_USE==0

/* stubs for efm32_mpu FIXME */

Expand Down
58 changes: 57 additions & 1 deletion include/unicore-mx/cm3/cortex.h
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Expand Up @@ -33,8 +33,11 @@

#include <stdbool.h>
#include <stdint.h>
#include <unicore-mx/common/cmsis.h>

/*---------------------------------------------------------------------------*/
#if __CMSIS_USE==0
#if defined ( __GNUC__ )
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
Expand All @@ -53,7 +56,6 @@ static inline void cm_disable_interrupts(void)
{
__asm__ volatile ("CPSID I\n");
}

/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
Expand Down Expand Up @@ -143,6 +145,60 @@ static inline uint32_t cm_mask_faults(uint32_t mask)
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
#elif defined ( __CC_ARM )

__attribute__((always_inline))
static inline
uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __asm("primask");
return(__regPriMask);
}

__attribute__((always_inline))
static inline
void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __asm("primask");
__regPriMask = (priMask);
}

#endif //defined ( __GNUC__ )

#else //__CMSIS_USE==0

#endif //__CMSIS_USE!=0

#if defined ( __CC_ARM )
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__enable_irq();
}

/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__disable_irq();
}

__attribute__((always_inline))
static inline
uint32_t cm_mask_interrupts(uint32_t mask)
{
register uint32_t old;
old = __get_PRIMASK();
__set_PRIMASK(mask);
return old;
}
#endif //defined ( __CC_ARM )

/**@}*/

Expand Down
6 changes: 6 additions & 0 deletions include/unicore-mx/cm3/memorymap.h
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Expand Up @@ -19,6 +19,7 @@
#define UNICOREMX_CM3_MEMORYMAP_H

/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
#include <unicore-mx/common/cmsis.h>

/* Private peripheral bus - Internal */
#define PPBI_BASE (0xE0000000U)
Expand All @@ -37,7 +38,9 @@

/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */

#if !(__CMSIS_USE)
#define SCS_BASE (PPBI_BASE + 0xE000)
#endif

/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */

Expand All @@ -57,6 +60,7 @@
/* SYS_TICK: System Timer */
#define SYS_TICK_BASE (SCS_BASE + 0x0010)

#if !(__CMSIS_USE)
/* NVIC: Nested Vector Interrupt Controller */
#define NVIC_BASE (SCS_BASE + 0x0100)

Expand All @@ -66,6 +70,8 @@
/* MPU: Memory protection unit */
#define MPU_BASE (SCS_BASE + 0x0D90)

#endif// !(__CMSIS_USE)

/* Those defined only on CM0*/
#if defined(__ARM_ARCH_6M__)
/* DEBUG: Debug control and configuration */
Expand Down
44 changes: 44 additions & 0 deletions include/unicore-mx/common/cmsis.h
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@@ -0,0 +1,44 @@
/*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
//* this header should provide CMSIS headers detection, to achieve compatibility on ones vs unicore headers

#ifndef UNICOREMX_CMSIS_COMPAT_H
#define UNICOREMX_CMSIS_COMPAT_H



#ifndef __CMSIS_USE
#if defined(__STM32F0xx_CMSIS_DEVICE_VERSION) \
|| defined(__STM32F1xx_CMSIS_DEVICE_VERSION)\
|| defined(__STM32F2xx_CMSIS_DEVICE_VERSION)\
|| defined(__STM32F3xx_CMSIS_DEVICE_VERSION)\
|| defined(__STM32F4xx_CMSIS_DEVICE_VERSION)\
|| defined(__STM32F7xx_CMSIS_DEVICE_VERSION)
#define __CMSIS_USE 1
#else
#define __CMSIS_USE 0
#endif
#endif

#if defined(HAL_MODULE_ENABLED) || defined(HAL_GPIO_MODULE_ENABLED)
#define __HAL_USE 1
#else
#define __HAL_USE 0
#endif


#endif
2 changes: 1 addition & 1 deletion include/unicore-mx/stm32/common/flash_common_f24.h
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Expand Up @@ -65,7 +65,7 @@

/* --- FLASH_CR values ----------------------------------------------------- */

#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_LOCK (1u << 31)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_STRT (1 << 16)
Expand Down
34 changes: 23 additions & 11 deletions include/unicore-mx/stm32/common/gpio_common_f234.h
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Expand Up @@ -43,19 +43,27 @@ specific memorymap.h header before including this header file.*/
@ingroup gpio_defines

@{*/
#if !(__HAL_USE) && !(__CMSIS_USE)
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
#define GPIOD GPIO_PORT_D_BASE
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOA_BASE GPIO_PORT_A_BASE
#define GPIOB_BASE GPIO_PORT_B_BASE
#define GPIOC_BASE GPIO_PORT_C_BASE
#define GPIOD_BASE GPIO_PORT_D_BASE
#define GPIOE_BASE GPIO_PORT_E_BASE
#define GPIOF_BASE GPIO_PORT_F_BASE
#endif

/**@}*/

/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */

/* Port mode register (GPIOx_MODER) */
#define GPIO_MODER(port) MMIO32((port) + 0x00)
#define GPIO_MODER(port) MMIO32(((uint32_t)port) + 0x00)
#define GPIOA_MODER GPIO_MODER(GPIOA)
#define GPIOB_MODER GPIO_MODER(GPIOB)
#define GPIOC_MODER GPIO_MODER(GPIOC)
Expand All @@ -64,7 +72,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_MODER GPIO_MODER(GPIOF)

/* Port output type register (GPIOx_OTYPER) */
#define GPIO_OTYPER(port) MMIO32((port) + 0x04)
#define GPIO_OTYPER(port) MMIO32(((uint32_t)port) + 0x04)
#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
Expand All @@ -73,7 +81,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)

/* Port output speed register (GPIOx_OSPEEDR) */
#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08)
#define GPIO_OSPEEDR(port) MMIO32(((uint32_t)port) + 0x08)
#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
Expand All @@ -82,7 +90,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)

/* Port pull-up/pull-down register (GPIOx_PUPDR) */
#define GPIO_PUPDR(port) MMIO32((port) + 0x0c)
#define GPIO_PUPDR(port) MMIO32(((uint32_t)port) + 0x0c)
#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
Expand All @@ -91,7 +99,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)

/* Port input data register (GPIOx_IDR) */
#define GPIO_IDR(port) MMIO32((port) + 0x10)
#define GPIO_IDR(port) MMIO32(((uint32_t)port) + 0x10)
#define GPIOA_IDR GPIO_IDR(GPIOA)
#define GPIOB_IDR GPIO_IDR(GPIOB)
#define GPIOC_IDR GPIO_IDR(GPIOC)
Expand All @@ -100,7 +108,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_IDR GPIO_IDR(GPIOF)

/* Port output data register (GPIOx_ODR) */
#define GPIO_ODR(port) MMIO32((port) + 0x14)
#define GPIO_ODR(port) MMIO32(((uint32_t)port) + 0x14)
#define GPIOA_ODR GPIO_ODR(GPIOA)
#define GPIOB_ODR GPIO_ODR(GPIOB)
#define GPIOC_ODR GPIO_ODR(GPIOC)
Expand All @@ -109,7 +117,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_ODR GPIO_ODR(GPIOF)

/* Port bit set/reset register (GPIOx_BSRR) */
#define GPIO_BSRR(port) MMIO32((port) + 0x18)
#define GPIO_BSRR(port) MMIO32(((uint32_t)port) + 0x18)
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
Expand All @@ -118,7 +126,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_BSRR GPIO_BSRR(GPIOF)

/* Port configuration lock register (GPIOx_LCKR) */
#define GPIO_LCKR(port) MMIO32((port) + 0x1c)
#define GPIO_LCKR(port) MMIO32(((uint32_t)port) + 0x1c)
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
Expand All @@ -127,7 +135,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_LCKR GPIO_LCKR(GPIOF)

/* Alternate function low register (GPIOx_AFRL) */
#define GPIO_AFRL(port) MMIO32((port) + 0x20)
#define GPIO_AFRL(port) MMIO32(((uint32_t)port) + 0x20)
#define GPIOA_AFRL GPIO_AFRL(GPIOA)
#define GPIOB_AFRL GPIO_AFRL(GPIOB)
#define GPIOC_AFRL GPIO_AFRL(GPIOC)
Expand All @@ -136,7 +144,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOF_AFRL GPIO_AFRL(GPIOF)

/* Alternate function high register (GPIOx_AFRH) */
#define GPIO_AFRH(port) MMIO32((port) + 0x24)
#define GPIO_AFRH(port) MMIO32(((uint32_t)port) + 0x24)
#define GPIOA_AFRH GPIO_AFRH(GPIOA)
#define GPIOB_AFRH GPIO_AFRH(GPIOB)
#define GPIOC_AFRH GPIO_AFRH(GPIOC)
Expand All @@ -151,10 +159,14 @@ specific memorymap.h header before including this header file.*/
/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
@ingroup gpio_defines
@{*/
#if !(__HAL_USE)
#define GPIO_MODE_INPUT 0x0
#endif
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
#if !(__HAL_USE)
#define GPIO_MODE_ANALOG 0x3
#endif
/**@}*/

/* --- GPIOx_OTYPER values ------------------------------------------------- */
Expand Down Expand Up @@ -208,7 +220,7 @@ specific memorymap.h header before including this header file.*/

/* --- GPIOx_LCKR values --------------------------------------------------- */

#define GPIO_LCKK (1 << 16)
//#define GPIO_LCKK (1ul << 16)
/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */

/* --- GPIOx_AFRL/H values ------------------------------------------------- */
Expand Down
7 changes: 7 additions & 0 deletions include/unicore-mx/stm32/common/gpio_common_f24.h
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Expand Up @@ -43,11 +43,18 @@ specific memorymap.h header before including this header file.*/
@ingroup gpio_defines

@{*/
#if !(__HAL_USE) && !(__CMSIS_USE)
#define GPIOG GPIO_PORT_G_BASE
#define GPIOH GPIO_PORT_H_BASE
#define GPIOI GPIO_PORT_I_BASE
#define GPIOJ GPIO_PORT_J_BASE
#define GPIOK GPIO_PORT_K_BASE
#define GPIOG_BASE GPIO_PORT_G_BASE
#define GPIOH_BASE GPIO_PORT_H_BASE
#define GPIOI_BASE GPIO_PORT_I_BASE
#define GPIOJ_BASE GPIO_PORT_J_BASE
#define GPIOK_BASE GPIO_PORT_K_BASE
#endif
/**@}*/

/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
Expand Down
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